The present invention relates generally to implantation systems used for fabrication of integrated circuits, and more particularly, to mechanisms for minimizing contamination of semiconductor wafers during implantation processes within an implantation chamber of the implantation system.
Referring to FIG. 1, a conventional implantation system 100 includes an ion beam source 102, an ion beam line 104, and an implantation chamber 106. Dopant ions are generated in the ion source 102, and the dopant ions travel through the ion beam line 104 to reach the implantation chamber 106. Upon reaching the implantation chamber 106, the dopant ions travel through an ion beam aperture 108 for entry into the implantation chamber 106. The dopant ions then travel though a plasma flood gun 110 which ensures uniform ionization of the dopant ions. The dopant ions are directed toward a semiconductor wafer placed on a wafer platen 112 with a voltage bias on the wafer platen 112.
The wafer platen 112 holds the semiconductor wafer to be implanted with the dopant ions within the implantation chamber 106. An ion beam profiler 114 within the implantation chamber 106 measures the dose of the dopant ions near the semiconductor wafer placed on the wafer platen 112. A dose cup 115 placed behind the wafer platen 112 is used to measure the dose of the dopant ions without the semiconductor wafer on the wafer platen 112 and without the wafer platen 112 within the implantation chamber 106 during characterizing and calibrating of the implantation system 100, as known to one of ordinary skill in the art of integrated circuit fabrication.
The conventional implantation system 100 with the components including the ion source 102, the ion beam line 104, the implantation chamber 106, the ion beam aperture 108, the plasma flood gun 110, the wafer platen 112, the ion beam profiler 114, and the dose cup 115 are known to one of ordinary skill in the art of integrated circuit fabrication. An example of such an implantation system is the model VIISta 80 commercially available from Varian Semiconductor Associates, Inc., headquartered in Gloucester, Mass.
Further referring to FIG. 1, in the prior art, a lot of a plurality of semiconductor wafers including a first semiconductor wafer 122 and a second semiconductor wafer 124 is processed within the implantation chamber 106. Each of the semiconductor wafers 122 and 124 is successively placed on the wafer platen 112 within the implantation chamber 106, and a respective implantation process is performed to implant each of the semiconductor wafers 122 and 124 with dopant ions from the ion source 102. For example, the first semiconductor wafer 122 is first placed on the wafer platen 112 within the implantation chamber 106, and a first implantation process is performed to implant the dopant ions into the first semiconductor wafer 122. After the first implantation process, the first semiconductor wafer 122 is removed from the implantation chamber 106, and the second semiconductor wafer 124 is placed on the wafer platen 112 within the implantation chamber 106. A second implantation process is performed to implant the dopant ions into the second semiconductor wafer 124.
A semiconductor wafer may have a material including a heavy metal compound deposited thereon. For example, oxides (SiO2) of such a heavy metal such as oxides of hafnium (Hf), zirconium (Zr), holmium (Ho), molybdenum (Mo), or gadolinium (Gd) are deposited on the semiconductor wafer. Such a heavy metal oxide instead of pure oxide is used to surround interconnect structures of integrated circuits to increase the dielectric constant of the insulating material surrounding the interconnect structures for minimized parasitic capacitance between the interconnect structures.
Referring to FIG. 1, the first semiconductor wafer 122 for example may have such a heavy metal compound deposited thereon. When ion beams hit such material on the first semiconductor wafer 122 placed on the wafer platen 112 within the implantation chamber 106 during the first implantation process, the ion beams may detach the heavy metal compound from the first semiconductor wafer 122 to contaminate the implantation chamber 106 with such heavy metal compound landing on inside surfaces of the implantation chamber 106 and on surfaces of the components within the implantation chamber including the ion beam aperture 108, the plasma flood gun 110 , the wafer platen 112, the ion beam profiler 114, and the dose cup 115. Such contamination is especially prevalent within implantation systems using a high implantation energy such as an implantation energy of about 40 KeV (Kilo-electron Volts).
Referring to FIG. 1, when the second semiconductor wafer 124 is placed on the wafer platen 122 of the implantation chamber 106, the heavy metal compound contaminants within the implantation chamber 106 from the first semiconductor wafer 122 may contaminate the second semiconductor wafer 124 during the second implantation process within the implantation chamber 106. For example, such heavy metal contaminants may contact and diffuse into a semiconductor wafer within the implantation chamber 106. Alternatively, such heavy metal contaminants may be incorporated into the dopant ion beam during an implantation process to be implanted into a semiconductor wafer. In addition, the heavy metal contaminant may hit the semiconductor wafer as back-scatter when the dopant ion beam strikes the heavy metal contaminants within the implantation chamber 106. In any case, as described in the journal article, Behavior of Molybdenum in Silicon Evaluated for Integrated Circuit Processing, by J. L. Benton, Journal of the Electrochemical Society, 146(5), 1929-1933, 1999, such heavy metal contaminants on a semiconductor wafer may deleteriously affect circuit performance of integrated circuit devices fabricated on the semiconductor wafer such as by increasing the leakage current of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or BJTs (Bipolar Junction Transistors).
Thus, a mechanism is desired for minimizing the level of contamination of the implantation chamber from such heavy metals on semiconductor wafers when semiconductor wafers are processed within the implantation chamber.
Accordingly, in a general aspect of the present invention, the implantation chamber and components within the implantation chamber are coated with additional material to minimize such heavy metal contamination within the implantation chamber.
In one embodiment of the present invention, for minimizing contamination of a semiconductor wafer to be implanted with a fabrication dopant within an implantation system, surfaces of an implantation chamber of the implantation system are coated by performing a first implantation process with a coating dopant before the semiconductor wafer is placed within the implantation chamber. In this manner, contaminants on the surfaces of the implantation chamber are substantially coated with the coating dopant. In addition, surfaces of components disposed within the implantation chamber are coated with the coating dopant during the first implantation process. Thus, contaminants on the surfaces of the components of the implantation chamber are substantially coated with the coating dopant during the first implantation process. After coating the surfaces of the implantation chamber and the components of the implantation chamber, the semiconductor wafer is placed within the implantation chamber, and a second implantation process is performed for doping the semiconductor wafer with the fabrication dopant within the implantation chamber.
In this manner, because the contaminants, on the surfaces of the implantation chamber and on the surfaces of the components of the implantation chamber, are substantially coated with the coating dopant, contamination of the second semiconductor wafer is minimized during the second implantation process.
In another embodiment of the present invention, for minimizing contamination of semiconductor wafers within an implantation system, surfaces of an implantation chamber of the implantation system are covered with a chamber shield. A first semiconductor wafer having contaminants thereon is placed within the implantation chamber, and a first implantation process is performed with the first semiconductor wafer within the implantation chamber. The chamber shield absorbs the contaminants from the first semiconductor wafer during the first implantation process. After the first implantation process, the first semiconductor wafer is removed from the implantation chamber, and the chamber shield is removed from the implantation chamber. A second semiconductor wafer is then placed within the implantation chamber, and a second implantation process is performed for doping the second semiconductor wafer with a fabrication dopant within the implantation chamber.
In a further embodiment of the present invention, components within the implantation chamber are also covered with component shields during the first implantation process. The component shields are removed from the components of the implantation chamber before the second semiconductor wafer is placed within the implantation chamber for the second implantation process.
In this manner, the contaminants are absorbed by the chamber shield and/or the component shields that are removed from the implantation chamber before the second semiconductor wafer is placed within the implantation chamber for the second implantation process. Thus, the second semiconductor wafer is exposed to minimized contaminants from the first semiconductor wafer during the second implantation process.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.